1. Field of the Invention
This invention generally relates to digital communications and, more particularly, to a system and method for rapidly achieving FEC synchronization through the use of an FEC flag character to mark the arrival of an FEC block.
2. Description of the Related Art
Ethernet messages, either octets of data or control information, are redundantly encoded for the purpose of maintaining DC balance, which is also referred to as running disparity (RD), and ensuring sufficient edge density. 8B/10B is a common RD-encoded format. 8-bit symbols are mapped into 10-bit symbols, coded to provide a sufficient number of state changes to permit clock recovery from the data stream and to ensure DC balance. 8B/10B coding is used in applications such as PCI Express, IEEE 1394b, Fibre Channel, Gigabit Ethernet, InfiniBand, and XAUI to name but a few. 64B/66B is a similar format where 64 symbols are mapped into a 66-bit word. Using a system that controls long-term DC-balance and edge density permits a data stream to be transmitted through a channel with a high-pass characteristic, and to be recovered with conventional clock and data recovery (CDR) units.
More explicitly, 64B/66B is encoded with 2 extra bits per 64 data bits, to detect the start of a 66-bit block. Two bits are used to provide a sufficiently unique value to find the start of a block. To maintain DC balance the value is either 10 or 01. 01 indicates that the block is data, and 10 indicates that the block is control. In addition to 64B/66B coding, Ethernet messages are typically encoded for FEC. FEC encoding creates parity information appended to the data, which is used to correct errors.
In accordance with IEEE Std. 802.3ap, a training pattern is run to help set the equalizers in the PHY, and then the FEC decoder searches for synchronization. The FEC is self-synchronizing and synchronization is not asserted until no errors are found. More explicitly, a typical FEC sync operation initially indicates that the FEC is out of sync, starts the capture of data, and performs error detection. Once a predetermined number of FEC blocks are received without errors, FEC synchronization is asserted. The FEC code that is used can take up to 446 microseconds to achieve synchronization.
In the case of the energy-efficient Ethernet being proposed in IEEE 802.3az, this long synchronization time would degrade performance as a device transitions from start-up in a low-power idle state to a full operational state. The FEC is shut off between communications to save power. The energy efficient Ethernet has a limited wake window that cannot tolerate a 446 microsecond synchronization time. Rather, the wake window must be in the order of 10B of microseconds.
It would be advantageous if an FEC encoded Ethernet data stream could be synchronized upon start-up in less than 100 microseconds.